Zero-crossing detectors are generally composed of a single comparator or of a plurality of cascaded comparators, the output of which changes state every time the input signal crosses the zero level. These circuits are widely employed in digital and in analog-digital systems. The figure-of-merit parameters of these circuits are typically: speed, gain, and the equivalent input offset.
Commonly, in communication systems that employ a peak detection technique, the first derivative of an input signal is fed to a zero-crossing detector. In this way, a digital signal may be obtained that is exactly synchronized with the zero-crossings of the signal representing the first derivative of the input signal and therefore with the positive and negative peaks of the input signal.
In this as in other applications, a net offset of the zero-crossing detector circuit produces an error of synchronization that is commonly referred to as "Pulse Pairing". This phenomenon is graphically depicted in FIG. 1. As may be observed from FIG. 1, for a sinusoidal input signal of frequency f and amplitude Vp, an equivalent input offset .DELTA.V produces a "Pulse Pairing" delay whose value .tau. is given by the following expression: ##EQU1##
It is evident that error, in terms of the "duty cycle" of the output signal, is introduced by the Pulse Pairing phenomenon. In the depicted example, the "duty cycle" of the output signal contains an error that is equivalent to 2.tau..
As mentioned above, a zero-crossing detector circuit may be constituted by a single comparator, for example the one depicted in FIG. 3. More often though, because of amplification requirements, the circuit is composed of a plurality of comparators connected in cascade. For example the circuit may be constituted by two comparators G1 and G2 in cascade, as schematically shown in FIG. 2. Of course, the two comparator stages G1 and G2 may have an identical circuit, as the one shown in FIG. 3.
For a comparator circuit as shown in FIG. 3, the standard deviation of the equivalent input offset is given by: ##EQU2## where: V.sub.trj,k is the standard deviation of the offset relative to the differential pairs T1-T2 and T3-T4;
.DELTA.R/3R is the standard deviation of the percentage error relative to the load resistances R; PA1 V.sub.t is the so-called thermal voltage that is equal to about 26 mV at room temperature.
By assuming the two stages G1 and G2 of the circuit of FIG. 2 are identical, they will have the same small signal gain Gj given by: ##EQU3## The equivalent input offset of the circuit will be given by the following expression: ##EQU4##
Notably, the offset of a differential pair of transistors depends primarily on the emitter area of the transistors and the biasing current. For example, in the case of an advanced CMOS process for high frequency, the dependence of the offset on the emitter area may be quantitatively derived from the curves of FIG. 4, which show the value of the standard deviation of the offset (.mu.V) as a function of the current density (.mu.A/.mu.m.sup.2) and respectively for a minimum emitter area (25 .mu.m.sup.2), for an emitter area equal to ten times (10.times.) the minimum area (250 .mu.m.sup.2) and for an emitter area equivalent to one hundred times (100.times.) the minimum emitter area (2500 .mu.m.sup.2). The same curves are shown in semilogarithmic form in FIG. 5, wherein the reference level 0 dB represents the offset of a minimum emitter area (25 .mu.m.sup.2) at low current density (which for the case shown is equivalent to 212 .mu.V).
On the basis of the above sample data, by supposing: EQU Area.sub.tr =25 .mu.m.sup.2 I.sub.1 =100 .mu.A I.sub.2 =50 .mu.A EQU R=4080 .OMEGA. .DELTA.R/R=.+-.0.5% EQU V.sub.tr1,2 =V.sub.tr3,4 =424 .mu.V
a standard deviation of the equivalent input offset may be calculated to be equal to: EQU .sigma..sub.offset =601 .mu.V giving a V.sub.off =3 .sigma..sub.offset =1,8 mV
By employing the above formula for calculating the Pulse Pairing with Vp=100 mV, f=9 MHz, one obtains: EQU Pulse Pairing=637 psec.
In many applications, for example in read/write channels of a mass memory system, such as a hard disk system, the working frequency of the circuit is often lower than 9 MHz, for example 4 MHz, and the input signal may have a remarkable amplitude, for example on the order of 500 mVp. In a relatively relaxed situation such as this, a circuit such as the one analyzed above would produce a Pulse Pairing of about 286 psec. which could be acceptable, depending on the application. By contrast, in case of high performance applications and of read/write channel specifications for advanced systems, more restrictive conditions may be imposed on Pulse Pairing besides those mentioned above. For example, the requirements of read/write channel specifications of new-generation systems may indicate operating conditions of Vp=100 mV, f.sub.min =9 MHz and a maximum Pulse Pairing limit of 250 psec.
These requirements would impose a maximum equivalent input offset value of 700 .mu.V.
By assuming again: EQU I.sub.1 =100 .mu.A I.sub.2 =50 .mu.A EQU R=4080 .OMEGA. .DELTA.R/R=.+-.0.5%
and a 1% precision of the current mirrors that feed the two emitter followers of the comparator circuit of FIG. 3, and by neglecting the contribution of a second comparator stage, the standard deviation of the offset of the differential pairs, suitable to satisfy the above mentioned specs, becomes: EQU V.sub.tr1,2 =V.sub.tr3,4 =150 .mu.V
As a consequence, the emitter area required for ensuring such an input offset limit at a bias current of 50 .mu.A is given by: EQU Area.sub.tr =100 .mu.m.sup.2
By assuming that the zero-crossing detector circuit is integrated in a mixed technology device, characterized by the formation of bipolar and CMOS structures in the same semiconducting substrate, for which the improvement of application techniques has permitted the decrease of the minimum definition sizes from 2 .mu.m for CMOS gates and 25 .mu.m.sup.2 for NPN emitters to 0.7 .mu.m and 1 .mu.m.sup.2, respectively, an emitter area one hundred times greater than the minimum area would have to be realized.
Therefore, while in a mature fabrication process the required increment of the emitter area would correspond to about four times the minimum emitter area, in an advanced fabrication process, the realization of the eight NPNs (four for each comparator stage of FIG. 3) so as to ensure the level of offset established by the specs would be equivalent to eight hundred minimum emitter areas.
It is evident that such a method of containing the offset within the limits dictated by the system specs, in the case of integrated circuits made with advanced fabrication processes would be very burdensome in terms of area requirements.
Alternative ways for reducing the offset have been proposed, for example by realizing parallel differential pairs, one of which would be variable so as to be periodically trimmable through a specific routine for controlling the offset. However, these systems are themselves complex and expensive to implement.